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rev.1.0, apr.05.2004, page 1 of 19 hd49330af/ahf cds/pga & 12-bit a/d converter rej03f0102-0100z (previous: ade-207-344) rev.1.0 apr.05.2004 description the hd49330af/ahf is a cmos ic that provides cds-pga analog processing (cds/pga) suitable for ccd camera digital signal processing systems together with a 12-bit a/d converter in a single chip. functions ? correlated double sampling ? pga ? offset compensation ? serial interface control ? 12-bit adc ? operates using only the 3 v voltage ? corresponds to switching mode of power dissipation and operating frequency power dissipation: 150 mw (typ), maximum frequency: 36 mhz power dissipation: 80 mw (typ), maximum frequency: 20 mhz ? adc direct input mode ? y-in direct input mode ? qfp 48-pin package features ? suppresses low-frequency noise output from ccd by the s/h type correlated double sampling. ? the s/h response frequency characteristics for the reference level can be adjusted using values of external parts and registers. ? high sensitivity is achieved due to the high s/n ratio and a wide coverage provided by a pg amplifier. ? feedback is used to compensate and reduce the dc offsets including the output dc offset due to pga gain change and the ccd offset in the cds (correlated double sampling) amplifier input. ? pga, standby mode, etc., is achieved via a serial interface. ? high precision is provided by a 12-bit-resolution a/d converter.
hd49330af/ahf rev.1.0, apr.05.2004, page 2 of 19 pin arrangement adcin av ss y in av dd bias blkc cdsin blkfb blksh av dd av ss av ss d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 36 35 27 34 33 32 31 30 29 28 26 25 12 10 3456789 1112 24 23 22 21 20 19 18 17 16 15 14 13 37 38 39 40 41 42 43 44 45 46 47 48 (top view) dv dd (nc) spsig spblk obp pblk dv dd dv dd adclk dv ss dv ss drdv dd vrm vrt vrb dv dd dv ss oeb dv dd dv dd dv ss cs sdata sck pin description pin no. symbol description i/o analog(a) or digital(d) 1 d0 digital output (lsb) o d 2 to 11 d1 to d10 digital output o d 12 d11 digital output (msb) o d 13 drdv dd output buffer power supply (3 v) ? d 14 dv ss digital ground (0 v) ? d 15 dv ss digital ground (0 v) ? d 16 adclk adc conversion clock input pin i d 17 dv dd digital power supply (3 v) ? d 18 dv dd digital power supply (3 v) ? d 19 pblk preblanking input pin i d 20 obp optical black pulse input pin i d 21 spblk black level sampling clock input pin i d 22 spsig signal level sampling clock input pin i d 23 nc no connection pin ? ? 24 dv dd output power supply (3 v) ? d 25 av ss analog ground (0 v) ? a 26 av ss analog ground (0 v) ? a 27 av dd analog power supply (3 v) ? a 28 blksh black level s/h pin ? a 29 blkfb black level fb pin ? a 30 cdsin cds input pin i a 31 blkc black level c pin ? a
hd49330af/ahf rev.1.0, apr.05.2004, page 3 of 19 pin description (cont.) pin no. symbol description i/o analog(a) or digital(d) 32 bias internal bias pin connect a 33 k ? resistor between bias and av ss . ? a 33 av dd analog power supply (3 v) ? a 34 y in y input pin ? a 35 av ss analog ground (0 v) ? a 36 adcin adc input pin ? a 37 vrm reference voltage pin 1 connect a 0.1 f ceramic capacitor between vrm and av ss . ? a 38 vrt reference voltage pin 3 connect a 0.1 f ceramic capacitor between vrt and av ss . ? a 39 vrb reference voltage pin 2 connect a 0.1 f ceramic capacitor between vrb and av ss . ? a 40 dv dd digital power supply (3 v) ? d 41 dv ss digital ground (0 v) ? d 42 oeb * 1 digital output enable pin ? d 43 dv dd digital power supply (3 v) ? d 44 dv dd digital power supply (3 v) ? d 45 dv ss digital ground (0 v) ? d 46 cs serial interface control input pin i d 47 sdata serial data input pin i d 48 sck serial clock input pin i d note: 1. with pull-down resistor.
hd49330af/ahf rev.1.0, apr.05.2004, page 4 of 19 input/output equivalent circuit pin name equivalent circuit digital output d0 to d11 din dv dd stby digital output digital input adclk, obp, spblk, spsig, cs, sck, sdata, pblk, oeb *1 digital input dv dd note: only oeb is pulled down to about 70 k ? . cdsin cdsin internally connected to vrt av dd adcin adcin internally connected to vrm av dd y in y in av dd ? + blksh, blkfb blkfb av dd blksh ? + vrt, vrm, vrb ? + ? + vrt vrm vrb av dd analog bias bias av dd
hd49330af/ahf rev.1.0, apr.05.2004, page 5 of 19 block diagram bias generator 33 34 32 43 45 44 17 26 28 29 35 2 3 4 5 6 7 8 11 42 9 10 19 18 16 31 12 bit adc d11 oeb vrb vrm vrt obp cdsin blksh 28 blkc 26 pblk 27 adcin 26 y in d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 blkfb cs sdata sck bias timing generator 19 18 16 adclk spblk spsig dv dd drdv dd av ss av dd 19 dv ss cds pga output latch circuit serial interface dc offset compensation circuit
hd49330af/ahf rev.1.0, apr.05.2004, page 6 of 19 internal functions functional description ? cds input ? ccd low-frequency noise is suppressed by cds (correlated double sampling). ? the signal level is clamped at 56 lsb to 304 lsb by resister during the ob period. ? gain can be adjusted using 10 bits of register (0.033 db steps) within the range from ?2.36 db to 31.40 db. * 1 ? adc input ? the center level of the input signal is clamped at 2048 lsb (typ). ? gain can be adjusted using 10 bits of register (0.00446 times steps) within the range from 0.57 times (?4.86 db) to 5.14 times (14.22 db). * 1 ? y-in input ? the input signal is clamped at 280 lsb (typ) by sync tip clamp. ? automatic offset calibration of pga and adc ? dc offset compensation feedback for ccd and cds ? pre-blanking ? cds input operation is protected by separating it from the large input signal. ? digital output is fixed at 32 lsb. ? digital output enable function note: 1. full-scale digital output is defined as 0 db (one time) when 1 v is input. operating description figure 1 shows cds/pga + adc function block. offset calibration logic dc offset feedback logic dac c3 cds amp pg amp adcin cdsin blkfb blksh gain setting (register) clamp data (register) obp sh amp blkc c4 c2 c1 vrt current dac 12-bit adc d0 to d11 figure 1 hd49330af/ahf functional block diagram 1. cds (correlated double sampling) circuit the cds circuit extracts the voltage differential between th e black level and a signal including the black level. the black level is directly sampled at c1 by using the spbl k pulse, buffered by the shamp, then provided to the cdsamp. the signal level is directly sampled at c2 by using the spsig pulse, and provided to cdsamp (see figure 1). the difference between these two signal levels is extracted by the cdsamp, which also operates as a programmable gain amplifier at the previous stage. the cds input is biased with vrt (2 v) during the spblk pulse validation period. during the pblk period, the above sampling and bias operation are paused.
hd49330af/ahf rev.1.0, apr.05.2004, page 7 of 19 2. pga circuit the pgamp is the programmable gain amplifier for the latter stage. the pgamp and the cdsamp set the gain using 10 bits of register. the equation below shows how the gain changes when register value n is from 0 to 1023. in cdsin mode: gain = (?2.36 db + 0.033 db) n (log linear). in adcin mode: gain = (0.57 times + 0.00446 times) n (linear). full-scale digital output is defined as 0 db (one time) when 1 v is input. 3. automatic offset calibration function and black-level clamp data setting the dac dc voltage added to the output of the pgamp is adjusted by automatic offset calibration. the data, which cancels the output offset of the pgamp and the input offset of the adc, and the clamp data (56 lsb to 304 lsb) set by register are added and input to the dac. the automatic offset calibration starts automatically after the reset mode set by register 1 is cancelled and terminates after 40000 clock cycles (when fclk = 20 mhz, 2 ms). 4. dc offset compensation feedback function feedback is done to set the black signal level input during the ob period to the dc standard, and all offsets (including the ccd offset and the cdsamp offset) are compensated for. the offset from the adc output is calculated during the ob period, and shamp feedback capacitor c3 is charged by the current dac (see figure 1). the open-loop differential gain ( ? gain/ ? h) per 1 h of the feedback loop is given by the following equation. 1h is the one cycle of the obp. ? gain/ ? h = 0.078/(fclk c3) (fclk: adclk frequency, c3: shamp external feedback capacitor) example: when fclk = 20 mhz and c3 = 1.0 f, ? gain/ ? h = 0.0039 when the pgamp gain setting is changed, the high-speed lead-in operation state is entered, and the feedback loop gain is increased by a multiple of n. loop gain multiplication factor n can be selected from 2 times, 4 times, 8 times, or 16 times by changing the register settings (see table 1). note that the open-loop differential gain ( ? gain/ ? h) must be one or lower. if it is two or more, oscillation occurs. the time from the termination of high-speed lead-in operation to the return of normal loop gain operation can be selected from 1 h, 2 h, 4 h, or 8 h. if the offset error is over 64 lsb, the high-speed lead-in operation continues, and when the offset error is 64 lsb or less, the operation returns to the normal loop-gain operation after 1 h, 2 h, 4 h, or 8 h depending on the register settings. see table 2. table 1 loop gain multiplication factor during high-speed lead-in operation table 2 high-speed lead-in operation cancellation time hgain-nsel (register settings) multiplication factor n hgstop-hsel (register settings) cancellation time [0] l h l h [1] l h h l 4 32 16 8 [0] l h l h [1] l h h l 1 h 8 h 4 h 2 h 5. pre-blanking function during the pblk input period, the csd input operation is separated and protected from the large input signal. the adc digital output is fixed to clamp data (56 to 304 lsb).
hd49330af/ahf rev.1.0, apr.05.2004, page 8 of 19 6. adc digital output control function the adc digital output includes the functions output enable, code conversion, and test mode. tables 3, 4 and 5 show the output functions and the codes. table 3 adc digital output functions operating mode adc digital output low-power wait state output hi-z normal operation pre-blanking normal operation pre-blanking test mode hi-z hi-z same as in table 4. d11 is inverted in table 4. d10 to d0 are inverted in table 4. d11 to d0 are inverted in table 4. output code is set up to clamp level. same as in table 5. d11 is inverted in table 5. d10 to d0 are inverted in table 5. d11 to d0 are inverted in table 5. output code is set up to clamp level. notes: 1. stby, test, linv, and minv are set by register. 2. mode setting for the oeb and the pblk are done by external input pins. 3. the polarity of the pblk pin when the register setting is spinv is low. x x h h h h l h h h h l x x x x h h l l l l h h h l h l l l h h h h l l l l h h h h l l l l h h h h l l l l h h h h l l l l h h x x l h l h x l h l h x l h l h x x l l h h x l l h h x l l h h x x l h x x x l h x h l h l stby d9 oeb d0 d1 d2 d3 d4 d5 d6 d7 d8 d11 d10 pblk minv linv test0 test1 table 4 adc output code output pin output codes steps 0 1 2 3 4 5 6 2047 2048 4092 4093 4094 4095 d1 l l h h l l h h l l l h h d0 l h l h l h l h l l h l h d2 l l l l h h h h l h h h h d7 l l l l l l l h l h h h h d5 l l l l l l l h l h h h h d4 l l l l l l l h l h h h h d3 l l l l l l l h l h h h h d6 l l l l l l l h l h h h h d8 l l l l l l l h l h h h h d9 l l l l l l l h l h h h h d10 l l l l l l l h l h h h h d11 l l l l l l l l h h h h h table 5 adc output code (test1) output pin output codes steps 0 1 2 3 4 5 6 2047 2048 4092 4093 4094 4095 d1 l l h h h h l l l h h l l d0 l h h l l h h l l l h h l d2 l l l l h h h l l l l l l d7 l l l l l l l l l l l l l d5 l l l l l l l l l l l l l d4 l l l l l l l l l l l l l d3 l l l l l l l l l l l l l d6 l l l l l l l l l l l l l d8 l l l l l l l l l l l l l d9 l l l l l l l l l l l l l d10 l l l l l l l h h l l l l d11 l l l l l l l l h h h h h
hd49330af/ahf rev.1.0, apr.05.2004, page 9 of 19 7. adjustment of black-level s/h response frequency characteristics the cr time constant that is used for sampling/hold (s/h) at the black level can be adjusted by changing the register settings, as shown in table 6. table 6 shsw cr time constant setting l [0] 2.20 nsec (72 mhz) 2.30 nsec (69 mhz) l [1] l [2] l 2.51 nsec (63 mhz) 2.64 nsec (60 mhz) 2.93 nsec (54 mhz) 3.11 nsec (51 mhz) 3.52 nsec (45 mhz) 3.77 nsec (42 mhz) [3] h [0] l [1] l [2] l [3] l [0] h [1] l [2] l [3] h [0] h [1] l [2] l [3] l [0] l [1] h [2] l [3] h [0] l [1] h [2] l [3] l [0] h [1] h [2] l [3] h [0] h [1] h [2] l [3] l [0] shsw-fsel (register setting) 4.40 nsec (36 mhz) 4.80 nsec (33 mhz) l [1] l [2] h cr time constant (typ) (cutoff frequency conversion) 5.87 nsec (27 mhz) 6.60 nsec (24 mhz) 8.80 nsec (18 mhz) 10.6 nsec (15 mhz) 17.6 nsec (9 mhz) 26.4 nsec (6 mhz) [3] h [0] l [1] l [2] h [3] l [0] h [1] l [2] h [3] h [0] h [1] l [2] h [3] l [0] l [1] h [2] h [3] h [0] l [1] h [2] h [3] l [0] h [1] h [2] h [3] h [0] h [1] h [2] h [3] blkc c4 31 the shamp frequency characteristics can be adjusted by changing the register settings and the c4 value of the external 31st pin. the settings are shown in table 7. values other than those shown in the table 7 cannot be used. 8. shsw-fsel (register setting) cr time constant (typ) (cutoff frequency conversion) table 7 shamp frequency characteristics setting 49 mhz 15000 pf (620 pf) 24 mhz 27000 pf (820 pf) 32 mhz 22000 pf (750 pf) sha-fsel (register setting) lopwr (register setting) note: upper line middle line lower line : shamp cutoff frequency (typ) : standard value of c4 (maximum value is not defined) : minimum value of c4 (do not set below this value) 56 mhz 18000 pf (360 pf) 116 mhz 10000 pf (270 pf) "lo" "hi" 75 mhz 13000 pf (300 pf) h [0] l [1] l [0] h [1] h [0] h [1]
hd49330af/ahf rev.1.0, apr.05.2004, page 10 of 19 timing chart figure 2 shows the timing chart when cdsin and adcin input modes are used. ~ d0 to d11 d0 to d11 note: the phases of spblk and spsig are those when the serial data spinv bit is set to low. 0 1 2 111213 n+1 n+2 n+11 n+12 n+13 n n ? 11 n ? 10 n ? 1n cdsin spblk spsig adclk n+2 n+10 n+11 n+12 n+13 n ? 10 n ? 11 n ? 1 adcin adclk n n+1 n n+1 n ? 12 ? when cdsin input mode is used ? when adcin input mode is used figure 2 output timing chart when cdsin and adcin input modes are used ? the adc output (d0 to d11) is output at the rising edge of the adclk in both modes. ? pipe-line delay is twelve clock cycles when cdsin is used and eleven when adcin is used. ? in adcin input mode, the input signal is sampled at the rising edge of the adclk.
hd49330af/ahf rev.1.0, apr.05.2004, page 11 of 19 detailed timing specifications detailed timing specifications wh en cdsin input mode is used figure 3 shows the detailed timing specifications when the cdsin input mode is used, and table 8 shows each timing specification. cdsin note: spblk vth (2) (3) spsig adclk (7) vth vth (8) (9) (10) black level signal level (4) (1) (5) (6) d0 to d11 1. when serial data spinv bit is set to low. (when the spinv bit is set to high, the polarities of the spblk and the spsig are inverted.) figure 3 detailed timing chart when cdsin input mode is used table 8 timing specifications when the cdsin input mode is used no. timing symbol min typ max unit (1) black-level signal fetch time t cds1 ? (1.5) ? ns (2) spblk low period * 1 t cds2 typ 0.8 1/4f clk typ 1.2 ns (3) signal-level fetch time t cds3 ? (1.5) ? ns (4) spsig low period * 1 t cds4 typ 0.8 1/4f clk typ 1.2 ns (5) spblk rising to spsig rising time * 1 t cds5 typ 0.85 1/2f clk typ 1.15 ns (6) spsig rising to adclk rising inhibition time * 1 t cds6 1 5 9 ns (7), (8) adclk t wh min./t wl min. t cds7, 8 11 ? ? ns (9) adclk rising to digital output hold time t chld9 3 7 ? ns (10) adclk rising to digital output delay time t cod10 ? 16 24 ns note: 1. spblk and spsig polarities when serial data spinv bit is set to low. obp detailed timing specifications figure 4 shows the obp detailed timing specifications. the ob period is from the fifth to the twelfth clock cycle after the ob pulse is input. the average of the black signal level is taken for eight input cycles during the ob period and becomes the clamp level (dc standard). cdsin obp note: ob pulse > 2 clock cycles when serial data obpinv bit is set to low (when the obpinv is set to high, the polarity of the obp is inverted.) ob period * 1 1. shifts 1 clock cycle depending on the obp input timing. n n+1 n+5 n+12 n+13 this edge is used, when obp pulse-width period is clamp-on. figure 4 obp detailed timing specifications
hd49330af/ahf rev.1.0, apr.05.2004, page 12 of 19 detailed timing specifica tions at pre-blanking figure 5 shows the pre-blanking detailed timing specifications. digital output (d0 to d11) adc data clamp level adc data pblk t pblk adclk 2 clocks adclk 12 clocks (shifts one clock cycle depending on the pblk input timing) when serial data spinv bit is set to low (when the spinv is set to high, the pblk polarity is inverted.) vth v ol v oh figure 5 detailed timing sp ecifications at pre-blanking detailed timing specifications wh en adcin input mode is used figure 6 shows the detailed timing chart when adcin input mode is used, and table 9 shows each timing specification. adcin (1) adclk d0 to d11 (2) vth v dd /2 (3) (5) (4) figure 6 detailed timing chart when adcin input mode is used table 9 timing specifications when adcin input mode is used no. timing symbol min typ max unit (1) signal fetch time t adc1 ? (6) ? ns (2), (3) adclk t wh min./t wl min. t adc2, 3 typ 0.85 1/2f adclk typ 1.15 ns (4) adclk rising to digital output hold time t ahld4 10 14.5 ? ns (5) adclk rising to digital output delay time t aod5 ? 23.5 31.5 ns detailed timing specifications fo r digital output-enable control figure 7 shows the detailed timing specifications for digital output enable control. when the oeb pin is set to high, output disable mode is entered, and the output state becomes high-z. digital output (d0 to d11) oeb t lz t zl t hz t zh dv dd /2 dv dd /2 dv dd 2 k ? 10 pf dv dd dv ss dv ss v ol t lz , t zl measurement load t hz , t zh measurement load v oh vth dv ss 10 pf 2 k ? dv ss figure 7 detailed timing specification s for digital output enable control
hd49330af/ahf rev.1.0, apr.05.2004, page 13 of 19 serial interface specifications resister 2 resister 0 resister 4 to 7 test mode (can not be used) resister 3 resister 1 low low to high low to high sha-fsel [0] (lsb) sha-fsel [1] (msb) shsw-fsel [0] (lsb) low: normal operation mode high: sleep mode slp low: normal operation mode high: standby mode stby low: cdsin input mode high: yin input mode csel low: cdsin input mode high: yin input mode ysel timing specifications table 10 serial data function list sck cs sdata di 00 di 01 di 02 di 03 di 04 di 05 di 06 di 07 di 08 di 09 di 10 di 11 di 12 di 13 di 14 di 15 latches sdata at sck rising edge data is determined at cs rising edge t int 1 t ho t su t int 2 f sck figure 8 serial interface timing specifications di 00 (lsb) di 01 low low high low low low low high high low high high di 02 x di 03 di 04 di 05 di 06 di 07 di 08 di 09 di 10 di 11 di 12 di 13 di 14 di 15 (msb) pga gain setting * 5 pga gain setting (lsb) * 5 pga gain setting * 5 pga gain setting * 5 pga gain setting * 5 pga gain setting * 5 pga gain setting * 5 pga gain setting * 5 pga gain setting * 5 pga gain setting (msb) * 5 cannot be used. * 8 cannot be used. * 8 cannot be used. * 8 cannot be used. * 8 cannot be used. * 8 cannot be used. * 8 low low low high high low t su t ho t int 1, 2 f sck 50 ns 50 ns 50 ns ? min ? ? ? 5 mhz max notes: 1. 2. 3. 4. 5. 6. 7. 8. 2 byte continuous communications. sdata is latched at sck rising edge. insert 16 clocks of sck while cs is low. data is invalid if data transmission is aborted during transmission. the gain conversion table differs in the cdsin input mode and the adcin input mode. stby: reference voltage generator circuit is in the operating state. slp: all circuits are in the sleep state. this bit is used for the ic testing, and cannot be used by the user. please do not set up in addition to "all low". this bit is used for the ic testing, and cannot be used by the user. it is set to the state on the right of a column when reset bit is set to low. the register 3 should transmit by setup on the right of a column. output mode setting (linv) output mode setting (minv) output mode setting (test0) shamp frequency character- istics switching shsw-fsel [1] shsw-fsel [2] shsw-fsel [3] (msb) shsw frequency character- istics switching hgstop-hsel [1] hgain-nsel [0] clamp-level [3] clamp-level [2] clamp-level [1] clamp-level [0] (lsb) clamp-level [4] (msb) hgstop-hsel [0] hgain-nsel [1] low: normal mode high: low power mode lopwr spinv, spsig/spblk/pblk inversion obpinv, obp inversion low: reset mode high: normal operation mode reset high-speed lead-in cancellation time high-speed lead-in gain multiplication yc-bias off output mode setting (test1) cannot be used. * 7 all low cannot be used. * 7 all low cannot be used. * 7 all low cannot be used. * 7 all low average4, 4 lines average
hd49330af/ahf rev.1.0, apr.05.2004, page 14 of 19 absolute maximum ratings (ta = 25 c) item symbol ratings unit power supply voltage v dd (max) 4.1 v analog input voltage v in (max) ?0.3 to av dd +0.3 v digital input voltage v i (max) ?0.3 to dv dd +0.3 v operating temperature topr ?10 to +75 c power dissipation pt(max) 400 mw storage temperature tstg ?55 to +125 c power supply voltage range vopr 2.85 to 3.3 v notes: 1. v dd indicates av dd and dv dd . 2. av dd and dv dd must be commonly connected outside the ic. when they are separated by a noise filter, the potential difference must be 0.3 v or less at power on, and 0.1 v or less during operation. electrical characteristics (unless othewide specified, ta = 25c, av dd = 3.0 v, dv dd = 3.0 v, and r bias = 33 k ? ) ? items common to cdsin and adcin input modes item symbol min typ max unit test conditions remarks power supply voltage range v dd 2.85 3.0 3.3 v f clk low 5.5 ? 20 mhz lopwr = high conversion frequency f clk hi 20 ? 36 mhz lopwr = low v ih dv dd 3.0 2.0 ? dv dd v v il 0 ? dv dd 3.0 0.8 v digital input pins other than cs, sck and sdata v ih2 dv dd 3.0 2.25 ? dv dd v digital input voltage v il2 0 ? dv dd 3.0 0.6 v cs, sck, sdata v oh dv dd ?0.5 ? ? v i oh = ?1 ma digital output voltage v ol ? ? 0.5 v i ol = +1 ma i ih ? ? 50 a v ih = 3.0 v i ih2 ? ? 250 a v ih = 3.0 v digital input current i il ?50 ? ? a v il = 0 v i ozh ? ? 50 a v oh = v dd digital output current i ozl ?50 ? ? a v ol = 0 v adc resolution res 12 12 12 bit adc integral linearity inl ? (8) ? lsbp-p f clk = 20 mhz adc differential linearity+ dnl+ ? 0.6 0.95 lsb f clk = 20 mhz *1 adc differential linearity? dnl? ?0.95 ?0.6 ? lsb f clk = 20 mhz *1 sleep current i slp ?100 0 100 a digital input pin is set to 0 v, output pin is open standby current i stby ? 3 5 ma digital i/o pin is set to 0 v t hz ? ? 100 ns t lz ? ? 100 ns t zh ? ? 100 ns digital output hi-z delay time t zl ? ? 100 ns r l = 2 k ? , c l = 10 pf see figure 7 notes: 1. differential linearity is the calculated difference in linearity errors between adjacent codes. 2. values within parentheses ( ) are for reference.
hd49330af/ahf rev.1.0, apr.05.2004, page 15 of 19 electrical characteristics (cont.) (unless othewide specified, ta = 25c, av dd = 3.0 v, dv dd = 3.0 v, and r bias = 33 k ? ) ? items for cdsin input mode item symbol min typ max unit test conditions remarks consumption current (1) i dd1 ? 54 65 ma lopwr = low f clk = 36 mhz consumption current (2) i dd2 ? 28 35 ma lopwr = high f clk = 20 mhz ccd offset tolerance range v ccd (?100) ? (100) mv timing specifications (1) t cds1 ? (1.5) ? ns timing specifications (2) t cds2 typ 0.8 1/4f clk typ 1.2 ns timing specifications (3) t cds3 ? (1.5) ? ns timing specifications (4) t cds4 typ 0.8 1/4f clk typ 1.2 ns timing specifications (5) t cds5 typ 0.85 1/2f clk typ 1.15 ns timing specifications (6) t cds6 1 5 9 ns timing specifications (7) t cds7 11 ? ? ns timing specifications (8) t cds8 11 ? ? ns timing specifications (9) t chld9 3 7 ? ns timing specifications (10) t cod10 ? 16 24 ns c l = 10 pf see table 8 clp(00) ? (56) ? lsb clp(09) ? (128) ? lsb clamp level clp(31) ? (304) ? lsb agc(0) ?4.4 ?2.4 ?0.4 db agc(256) 4.1 6.1 8.1 db agc(512) 12.5 14.5 16.5 db agc(768) 21.0 23.0 25.0 db pga gain at cds input agc(1023) 29.4 31.4 33.4 db note : values within parentheses ( ) are for reference. ? items for adcin input mode item symbol min typ max unit test conditions remarks consumption current (3) i dd3 ? 39 49 ma lopwr = low f clk = 36 mhz consumption current (4) i dd4 ? 21 26 ma lopwr = high f clk = 20 mhz timing specifications (11) t adc1 ? (6) ? ns timing specifications (12) t adc2 typ 0.85 1/2f adclk typ 1.15 ns timing specifications (13) t adc3 typ 0.85 1/2f adclk typ 1.15 ns timing specifications (14) t ahld4 ? 14.5 ? ns timing specifications (15) t aod5 ? 23.5 31.5 ns c l = 10 pf see table 9 input current at adc input iin cin ?110 ? 110 a v in = 1.0 v to 2.0 v clamp level at adc input of2 ? (2048) ? lsb clamp level at yin input of1 ? (280) ? lsb gsl(0) 0.45 0.57 0.72 times gsl(256) 1.36 1.71 2.16 times gsl(512) 2.27 2.86 3.60 times gsl(768) 3.18 4.00 5.04 times pga gain at adc input gsl(1023) 4.08 5.14 6.47 times note : values within parentheses ( ) are for reference.
hd49330af/ahf rev.1.0, apr.05.2004, page 16 of 19 operation sequence at power on v dd hd49330af/ahf serial data transfer reset bit reset = "low" (reset mode) reset = "high" (reset cancellation) must be stable within the operating power supply voltage range spblk spsig adclk obp etc. start control of tg and camera dsp 0 ms or more (1) register 2 setting (2) register 2 setting (3) register 0, 1 and 3 settings : set all bits in register 2 to the usage condition, and set the reset bit to low. : cancel the reset mode by setting the register 2 reset bit to high. do not change other register 2 settings. offset calibration starts automatically. : after the offset calibration is terminated, set registers 0, 1 and 3. (1) register 2 setting (2) register 2 setting (3) registers 0, 1 and 3 settings 0 ms or more 0 ms or more 2 ms or more 2 ms or more ends after 40000 clock cycles automatic offset calibration the following describes the above serial data transfer. for details on registers 0, 1, 2, and 3, refer to table 10. offset calibration (automatically starts after reset cancellation)
hd49330af/ahf rev.1.0, apr.05.2004, page 17 of 19 notice for use 1. careful handling is necessary to prevent damage due to static electricity. 2. this product has been developed for consumer applications, and should not be used in non-consumer applications. 3. as this ic is sensitive to power line noise, the ground impedance should be kept as small as possible. also, to prevent latchup, a ceramic capacitor of 0.1 f or more an d an electrolytic capacitor of 10 f or more should be inserted between the ground and power supply. 4. common connection of av dd and dv dd should be made off-chip. if av dd and dv dd are isolated by a noise filter, the phase difference should be 0.3 v or less at power-on and 0.1 v or less during operation. 5. if a noise filter is necessary, make a common connection after passage through the filter, as shown in the figure below. hd49330af/ahf av ss dv ss av dd dv dd noise filter analog +3.0v hd49330af/ahf dv ss av ss dv dd av dd 100 h 0.01 f noise filter example of noise filter digital +3.0v 0.01 f 6. connect av ss and dv ss off-chip using a common ground. if there are separate analog system and digital system set grounds, connect to the analog system. 7. when v dd is specified in the data sheet, this indicates av dd and dv dd . 8. no connection (nc) pins are not connected inside the ic , but it is recommended that they be connected to power supply or ground pins or left open to prevent crosstalk in adjacent analog pins. 9. to ensure low thermal resistance of the package, a cu-type lead material is used. as this material is less tolerant of bending than fe-type lead material, careful handling is necessary. 10. the infrared reflow soldering method should be used to mount the chip. note that general heating methods such as solder dipping cannot be used. 11. serial communication should not be performed during the effective video period, since this will result in degraded picture quality. also, use of dedicated ports is recommended for the sck and sdata signals used in the hd49330af. if ports are to be shared with another ic, picture quality should first be thoroughly checked. 12. at power-on, automatic adjustment of the offset voltage generated from pga, adc, etc., must be implemented in accordance with the power-on operating sequence (see page 16).
hd49330af/ahf rev.1.0, apr.05.2004, page 18 of 19 example of recommended external circuit r11 100 r12 100 r13 100 r10 100 c20 0.1 c18 0.1 c19 0.1 c17 0.1 l1 47 ? at cds input notes: 1. for c4, see table 5. 2. for c3, see page 8 "dc offset compensation feedback function". unit: r: ? c: f 23 26 27 28 29 30 31 32 33 34 c4* 1 c14 0.1 r15 33 k c15 0.1 35 36 25 11 10 9 8 7 6 5 4 3 2 1 12 16 15 14 13 17 18 19 20 21 22 24 38 45 46 47 48 44 43 42 41 40 39 37 serial data input gnd from timing generator from ccd out note: external circuit is same as above except for adc/y input. 3.0 v 3.0 v to camera signal processor to camera signal processor c21 0.1 c22 0.1 c20 0.1 c18 0.1 c19 0.1 c17 0.1 c21 0.1 c22 0.1 c13 0.1 c1 1 c3 * 2 1 c10 0.1 c11 0.1 c12 0.1 c11 0.1 c12 0.1 r15 33 k c16 47/6 c21 47/6 l2 47 r14 100 hd49330af/ahf (cds/pga+adc) l1 47 ? at adc/yin input vrm vrt vrb dv dd dv ss oeb dv dd dv dd dv ss cs sdata sck d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 dv dd (nc) spsig spblk obp pblk dv dd dv dd adclk dv ss dv ss drdv dd av ss av ss av dd blksh blkfb cdsin blkc bias av dd y in av ss adcin 23 26 27 28 29 30 31 32 33 34 c15 0.1 35 36 25 11 10 9 8 7 6 5 4 3 2 1 12 16 15 14 13 17 18 19 20 21 22 24 38 45 46 47 48 44 43 42 41 40 39 37 serial data input gnd from timing generator c14 0.1 c13 0.1 c2 2.2/16 c16 47/6 c21 47/6 l2 47 hd49330af/ahf (cds/pga+adc) + ? c23 0.47 with y input av ss av ss av dd blksh blkfb cdsin blkc bias av dd y in av ss adcin d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 dv dd (nc) spsig spblk obp pblk dv dd dv dd adclk dv ss dv ss drdv dd vrm vrt vrb dv dd dv ss oeb dv dd dv dd dv ss cs sdata sck with adc input
hd49330af/ahf rev.1.0, apr.05.2004, page 19 of 19 package dimensions package code jedec jeita mass (reference value) fp-48c ? conforms 0.2 g *dimension including the plating thickness base material dimension 9.0 0.2 7.0 *0.21 0.05 0.08 36 25 112 37 48 24 13 0.5 9.0 0.2 0.10 1.00 0? ? 8? 0.50 0.10 *0.17 0.05 1.70 max m 0.75 0.75 0.19 0.04 1.40 0.15 0.04 0.13 +0.09 ?0.05 as of january, 2003 unit: mm
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